In current memory systems, data stored in volatile memories (e.g., DRAM) must be periodically refreshed to compensate for inherent leakage of capacitors in memory cells. In essence, refreshing includes, for example, reading data out of each row of memory and subsequently writing the data back to the same respective row. As a result, the original charge level on each capacitor is restored and data preserved.
While many approaches for using memory refreshes to compensate for leakage are well known in the art, these approaches have struggled when applied to the increasingly demanding operating speeds and applications of memories today. For example, in some instances, a particular row or rows of memory may be repeatedly accessed at a high frequency. Data stored by memory cells of rows physically adjacent the repeatedly accessed row of memory may be degraded before normal refresh operations are performed to preserve the data of those adjacent rows. That is, due to coupling effects, cell to cell leakage may increase, and the repetitive accesses may degrade data of rows physically adjacent the repetitively accessed row or rows.